Platform-related Limitations to Efficiency in Standard Clock Simulation on Sequential Machines

نویسندگان

  • Craig M. Barnhart
  • Jeffrey E. Wieselthier
  • Anthony Ephremides
چکیده

Standard Clock (SC) simulation is an efficient form of discreteevent simulation that is applicable to systems with exponential interevent times. It achieves its efficiency by using a common event stream to construct, on sequential or parallel machines, many sample paths in parallel. However, on sequential machines the efficiency is limited by two factors: (1) A fundamental simulation method-related limitation predicts an upper bound on achievable speedup that is determined by the ratio of the event generation time to the sample path update time. (2) There is also a platformrelated limitation to efficiency that is a result of increasing memory requirements as the SC simulation is scaled. In this paper, we develop a slightly modified form of SC simulation that mitigates the loss of efficiency caused by memory management expenses. With this approach, groups of events, rather than individual events, are passed to each sample path so that the cache-break expense is amortized over the event group size.

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تاریخ انتشار 1995